VHDL电子琴的设计程序.doc

附录 程序清单： 顶层模块程序： library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity top is Port ( clk32MHz :in std_logic; --32MHz系统时钟 handTOauto : in std_logic; --键盘输入/自动演奏 code1 :out std_logic_vector(6 downto 0); --音符显示信号 index1 :in std_logic_vector(7 downto 0); --键盘输入信号 high1 :out std_logic; --高低音节信号 spkout :out std_logic); --音频信号 end top; architecture Behavioral of top is component automusic Port ( clk :in std_logic; Auto: in std_logic; index2:in std_logic_vector(7 downto 0); index0 : out std_logic_vector(7 downto 0)); end component; component tone Port ( index : in std_logic_vector(7 downto 0); code : out std_logic_vector(6 downto 0); high : out std_logic; tone0 : out integer range 0 to 2047); end component; component speaker Port ( clk1 : in std_logic; tone1 : in integer range 0 to 2047; spks : out std_logic); end component; signal tone2: integer range 0 to 2047; signal indx:std_logic_vector(7 downto 0); begin u0:automusic port map(clk=clk32MHZ,index2=index1,index0=indx,Auto=handtoAuto); u1: tone port map(index=indx,tone0=tone2,code=code1,high=high1); u2: speaker port map(clk1=clk32MHZ,tone1=tone2,spks=spkout); end Behavioral; 自动演奏模块程序 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity automusic is Port ( clk,Auto : in std_logic; --系统时钟；键盘输入/自动演奏 index2 : in std_logic_vector(7 downto 0); --键盘输入信号 index0 : out std_logic_vector(7 downto 0));--音符信号输出 end automusic; architecture Behavioral of automusic is signal count0:integer range 0 to 31;--change signal clk2:std_logic; begin pulse0:process(clk,Auto)