如何提高layout效率.ppt

Improve the efficiency of layout 蒋林利 * PITEL Display.drf .tf eum6179 Master library pm eum6167 eum6179 …… cdl drc lvs layout lpe optimized project manage cd pm/eum6167/layout icfb optimized project manage Note: Every project have its own folder Every folder should be named by lowercase The display file should be named ‘display.drf’ It’s advised to startup ‘icfb’ in folder ‘layout’ Library top cell should share the same name Just the project library the master library should be put in ‘layout’ optimized project manage Library path manage Too many useless library ! optimized project manage Library path manage The useful library also can be write into the path editor Note: To find out cds.lib in the ‘layout’ folder And delete the first line Such as ‘INCLUDE /home/test/cds.lib’ optimized project manage Library path manage Take care of the popedom Too many paths should be delete. Master library layout Display.drf .tf eum6167 Master library Master library via1 contact NMOS_pcell PMOS_pcell resistance via2 W=4um W=3um Identical size!!! Minimal size!!! Different size!!! optimized project manage Master library If there are other devices such as BJT、VDMOS and so on just add them in If you meet another project with the same Process technology, You can just copy the master library to you new project folder And write its path into the path editor! Note: Not stream in, but just copy! Make the contact via just the same size as long as the design rule allows Just use the instances in the master library, please don’t draw them by yourself! Other details Remember 5~6 design rules: space between metals, space between diffusions, space between wells and diffusion…… Use array when you instance the cells or copy Use the layer generation to grow new layers 在剩余两三个子模块未画的时候开始绕整体 （这些模块通常含电容、电阻） Use Δx、 Δy without the ‘ruler’ Use F4 without strench 1.当进行稍微大的修改时，请保留原文件，在复制出来的文件里进行修改 备份！！ 2.不要随意删除目前认为无用的cell，也许别人正好调用了此模块，甚至也许你的designer过几天又让你改回原来的电路结