有限状态机进行时序逻辑.doc

看北航夏宇闻老师写的《verilog 数字系统设计教程》中利用有限状态机进行时序逻辑的设计一个练习，发觉状态机的设计优点问题。检测的目标序列是 10010，原代码是这样设计的。原文的设计程序-----------------------------------------------------------------------------------------------------------------------module test(clock,reset,signalin,signalout);??? input clock,signalin,reset;??? output signalout;??? reg [2:0] state;??????? parameter???? ??? idle = 3d0,??? ??? a = 3d1,??? ??? b = 3d2,??? ??? c = 3d3,??? ??? d = 3d4,??? ??? e = 3d5,??? ??? f = 3d6,??? ??? g = 3d7;??????? assign signalout = (state == e signalin == 0)?1:0;??????? always@(posedge clock)??? ??? if(!reset)??? ??? ??? begin??? ??? ??? ??? state = idle;??? ??? ??? end??? ??? else??? ??? ??? begin??? ??? ??? ??? casex(state)??? ??? ??? ??? ??? idle:??? ??? ??? ??? ??? ??? begin??? ??? ??? ??? ??? ??? ??? if(signalin == 1)??? ??? ??? ??? ??? ??? ??? ??? state = a;??? ??? ??? ??? ??? ??? ??? else??? ??? ??? ??? ??? ??? ??? ??? state = idle;??? ??? ??? ??? ??? ??? end??? ??? ??? ??? ??? a:??? ??? ??? ??? ??? ??? begin??? ??? ??? ??? ??? ??? ??? if(signalin == 0)??? ??? ??? ??? ??? ??? ??? ??? state = b;??? ??? ??? ??? ??? ??? ??? else??? ??? ??? ??? ??? ??? ??? ??? state = a;??? ??? ??? ??? ??? ??? end??? ??? ??? ??? ??? b:??? ??? ??? ??? ??? ??? begin??? ??? ??? ??? ??? ??? ??? if(signalin == 0)??? ??? ??? ??? ??? ??? ??? ??? state = c;??? ??? ??? ??? ??? ??? ??? else??? ??? ??? ??? ??? ??? ??? ??? state = f;??? ??? ??? ??? ??? ??? end??? ??? ??? ??? ??? c:??? ??? ??? ??? ??? ??? begin??? ??? ??? ??? ??? ??? ??? if(signalin == 1)??? ??? ??? ??? ??? ??? ??? ??? state = d;??? ??? ??? ??? ??? ??? ??? else??? ??? ??? ??? ??? ??? ??? ??? state = g;??? ??? ??? ??? ??? ??? end??? ??? ??? ??? ??? d:??? ??? ??? ??? ??? ??? begin??? ??? ??? ??? ??? ??? ??? if(signalin == 0)??? ??? ??? ??? ??? ??? ??? ??? state = e;??? ??? ??? ??? ??? ??? ??? else??? ??? ??? ??? ??? ??? ??? ??? state = a;??? ??? ??? ??? ??? ??? end??? ??? ??? ??? ??? e:??? ???