FPGA可编程逻辑器件芯片5SGSED8K1F40I2N中文规格书.pdf
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Data Test Registers
Data Test Command Register(DTEST_COMMAND)
31302928272625242322212019181716
0xFFE00300 × × × ×
xxx× × × × × x× × × Reset = Undefined
Access way/instruction
Address Bit 11
0 - Access WayO/Instruction bit 11=0 Sub-bank Access[1:0]
1-Access Way1/Instruction bit 11=1 (SRAM ADDR[13:12])
Data/Instruction Access 00-Access sub-bank 0
01 -Access sub-bank 1
0-Access Data 10-Access sub-bank 2
1-Access Instruction
11-Access sub-bank 3
Data Bank Access
0-Access Data Bank A/instruction memory OxFFAO 0000
1-Access Data Bank B/ instruction memory OxFFAO 8000
1514131211109876543210
xx× xxx× x× x× xxxxx
Bead/rite Access
Data Cache Select/
Address Bit 14 0.Read access
0- Reserved for data memory Access/ 1-Write access
Instruction bit 14=0 Array Access
1-Selects Data Cache Bank/ 0-Access tag array
Instruction bit 14=1 1 ·Access data array
Set Index[5:0]———
Selects one of 64 sets
Double Word Index[1:0]
Selects one of four 64-bit
double words in a 256-bit line
Figure 3-13. Data Test Command Register
原厂原装
IT47H128M16RT-25EIT CMICRON BGA 9133
MT47H128M16RT-25EIT:C FBGA 598
MICRON
原厂原装
MICRON FBGA84
IT47H128M16RT-25E-IT:C原厂原装 1000
IT47H128M16RT-25EXIT:C 原厂原装 FBGA
Micron 60
MT47H128M16RT-3 I
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