基于VHDL语的数字钟设计.doc
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一．程序代码及其仿真：
cnt60子模块代码：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY V_cnt60 IS
PORT ( clk :IN std_logic;
Q0,Q1,Q2,Q3,Q4,Q5,Q6,QC :OUT std_logic);
END V_cnt60;
ARCHITECTURE func OF V_cnt60 IS
SIGNAL count1 :std_logic_vector(3 downto 0);
SIGNAL count2 :std_logic_vector(3 downto 0);
SIGNAL carryin:std_logic;
BEGIN
Q0 = count1(0);
Q1 = count1(1);
Q2 = count1(2);
Q3 = count1(3);
Q4 = count2(0);
Q5 = count2(1);
Q6 = count2(2);
QC = carryin;
process(clk)
BEGIN
if (clkevent AND clk=1) then
carryin=0;
if(count1=1001)then
count1=0000;
count2=count2+1;
else
count1=count1+1;
END if;
if(count2=0101AND count1=1001)then
count2=0000;
count1=0000;
carryin=1;
END if;
END if;
END process;
END func;
cnt60仿真波形：
cnt24子模块代码：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY V_cnt24 IS
PORT ( clk :IN std_logic;
Q0,Q1,Q2,Q3,Q4,Q5:OUT std_logic);
END V_cnt24;
ARCHITECTURE func_cnt24 OF V_cnt24 IS
SIGNAL count1 :std_logic_vector(3 downto 0);
SIGNAL count2 :std_logic_vector(3 downto 0);
SIGNAL carryin:std_logic;
BEGIN
Q0 = count1(0);
Q1 = count1(1);
Q2 = count1(2);
Q3 = count1(3);
Q4 = count2(0);
Q5 = count2(1);
process(clk)
BEGIN
if (clkevent and clk=1) then
if(count1=1001)then
count1=0000;
count2=count2+1;
else
count1=count1+1;
END if;
if(count2=0010 AND count1=0011)then
count2=0000;
count1=0000;
END if;
END if;
END process;
END func_cnt24;
cnt24仿真波形：
cnt1000字模块代码：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity V_cnt1000 is
port( clk :in std_lo
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