LiberoIDEv9.1中MODELSIM仿真简述.docx

Libero IDE v9.1中MODELSIM仿真简述： 写好要测试的VHDL代码 cnt6.vhd； 针对cnt6.vhd写激励文件testbench.vhd, testbench同样也是VHDL代码； 进入modelsim后首先建立库文件WORK，具体参见相关教程； 其次建立工程PROJECT，具体参见相关教程； Compile cnt6.vhd和testbench.vhd 设置runtime options 运行周期1us Start simulation，选择激励文件和resolution后点OK 在OBJECTS窗口add signal run 观察WAVE窗口为仿真结果 以下代码已测试无误，全部来源网页： /wangjun403/article/details/6246830 写简单的testbench 六进制计数器的代码 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; --use ieee.std_logic_unsigned.all; entity cnt6 is port (clr,en,clk :in std_logic; q :out std_logic_vector(2 downto 0) ); end entity; architecture rtl of cnt6 is signal tmp :std_logic_vector(2 downto 0); begin process(clk) -- variable q6:integer; begin if(clkevent and clk=1) then if(clr=0)then tmp=000; elsif(en=1) then if(tmp=101)then tmp=000; else tmp=unsigned(tmp)+1; end if; end if; end if; q=tmp; -- qa=q(0); -- qb=q(1); -- qc=q(2); end process; end rtl; 六进制计数器testbench的代码 library ieee; use ieee.std_logic_1164.all; entity cnt6_tb is end cnt6_tb; architecture rtl of cnt6_tb is component cnt6 port( clr,en,clk :in std_logic; q :out std_logic_vector(2 downto 0) ); end component; signal clr :std_logic:=0; signal en :std_logic:=0; signal clk :std_logic:=0; signal q :std_logic_vector(2 downto 0); constant clk_period :time :=20 ns; begin instant:cnt6 port map ( clk=clk,en=en,clr=clr,q=q ); clk_gen:process begin wait for clk_period/2; clk=1; wait for clk_period/2; clk=0; end process; clr_gen:process begin clr=0; wait for 30 ns; clr=1; wait; end process; en_gen:process begin en=0; wait for 50n